patch-2.4.20 linux-2.4.20/arch/mips/kernel/irq_cpu.c

• Lines: 9
• Date: Thu Nov 28 15:53:10 2002
• Orig file: linux-2.4.19/arch/mips/kernel/irq_cpu.c
• Orig date: Fri Aug 2 17:39:43 2002

diff -urN linux-2.4.19/arch/mips/kernel/irq_cpu.c linux-2.4.20/arch/mips/kernel/irq_cpu.c
@@ -13,7 +13,7 @@
 /*
  * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
  * level triggered (i.e., cannot be cleared from CPU; must be cleared from
- * device).  The first two are software interrupts.  The last one is 
+ * device).  The first two are software interrupts.  The last one is
  * usually the CPU timer interrupt if counter register is present or, for
  * CPUs with an external FPU, by convention it's the FPU exception interrupt.
  *